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TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 1 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 sir endec for irda ? applications integrated interface circuit description the TOIM5232 endec ic provides proper pulse shaping for the sir irda front end infrared transceivers as of the 4000-series. ? for transmitting the TOIM5232 shortens the rs232 output signal to irda compatible electrical pulses to drive the infrared transmitter. in the receive mode, the TOIM5232 stretches the received infrared pulses to the proper bit width depending on the operating bit ra te. the irda bit rate varies from 2.4 kbit/s to 115.2 kbit/s. ? the TOIM5232 is using a crystal clock 3.6864 mhz (< 7.5 mhz) for its pulse stretching and shortening. the clock is generated by the internal oscillator. an external clock can be used, too. the TOIM5232 is programmable to operate from 1200 bit/s to 115.2 kbit/s by the communication software through the rs232 port. the output pulses are software programmable as either 1.627 s or 3/16 of bit time. the typi cal power consumption is very low with about 10 mw in operational state and in the order of a few microwatts in standby mode. TOIM5232 in the tiny qfn-20 package is the space-minimized version of TOIM5232. ulc technology: high performance ga te array package using multiple metal layer cmos technology featuring sub-micron channel lengths (0.35 m). features ? pulse shaping function according irda sir physical layer ? directly interfaces the sir transceiver to a rs232 port ? qfn-20 - package, 4 mm x 4 mm x 0.75 mm ? low operating current ? programmable baud clock generator (1200 hz to 115.2 khz), 13 baud rates ? 3/16 bit pulse duration or 1.627 s pulse selectable ? for 2.7 v to 3.6 v operation voltage, 5 v tolerant inputs ? qualified for lead (pb)-free and sn/pb solder processing (msl3) ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 ? ? ? ? ? ? ? ? ? ? ? ? ? 20810 parts table part description qty/reel TOIM5232-tr3 sir endec for irda application 6000 pcs product summary part number data rate (kbit/s) dimensions h x l x w (mm x mm x mm) link distance (m) operating voltage (v) idle supply current (ma) TOIM5232 1.2 to 115 4 x 4 x 0.75 - 2.7 to 3.6 2
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 2 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 block diagram notes (1) crystal should be connected as shown in the block diagram or in the recommen ded application circuit. connect a 100 k ? resistor from pin 4 to pin 5 and from pin 4 and pin 5 a 22 pf capacitor to ground, respectively. when an external clock is available connect it t o pin 4 leaving pin 5 open. the external resistor of 100 k ? is used to accelerate the star t of the oscillation af ter reset or power-on. the value depends on the q of the resonator. with lo w q resonators no resistor is ne eded. the start-up time of the oscillator is between 30 s (wi th piezo resonators) and above 2 ms with high q quartzes. (2) this condition is fulfilled with all vishay ir transceivers. pin assignment and description pin number symbol discription i/o active 1 rd_232 received signal data output of stretched signal to the rs232 rxd line (using level converter). ohigh 2 td_232 input of the signal to be transmitted from the rs232 port txd line (passing the level converter). ihigh 3 v cc_sd this pin can be used to shut down a transceiver (e.g., tfdx4xxx). output polarity: inverted reset input. olow 4x1 crystal input clock, 3.6864 mhz nominal for 9.6 kbit/s default setting. inpu t for external clock (1) . option: 7.3728 mhz for 19.2 kbit/s default operation. i 5x2 crystal (1) i 7 gnd ground in common with the rs232 port and irda transceiver ground 9 td_led transmit led indicator driver. use 180 ? current limiting resistor in series to led to connect to v cc (v cc = 3.3 v). olow 10 rd_led receive led indica tor driver. use 180 ? current limiting re sistor in series to led to connect to v cc (v cc = 3.3 v). olow 12 s1 user programmable bit. can be used to turn on/ off a front-end infrared transceiver (e.g., an infrared module at the adapter front). olow 13 s2 user programmable bit. can be used to turn on/ off a front-end infrared transceiver (e.g., an infrared module at the adapter back). olow 14 td_ir data output of shortened signal to the infrared transceiver. o high 16 rd_ir data input from the infrared transceiver, min. pulse duration 1.63 s (2) ilow 17 v cc supply voltage i 1 8 reset resets all internal registers. initially must be hi gh (1) to reset internal registers. when high, the TOIM5232 sets the irda default bit rate of 9600 bit/s, sets pulse width to 1.627 s. the v cc_sd output is simply an inverted reset signal which allows shutdown of a tfdx4x00 transceiver when appl ying the reset signal to the to im5232. when using devices with external sd like tfdu4101, th e reset line can be used di rectly as shutdown signal. reset pin can be controlled by either the rts or dtr line through rs232 leve l converter. minimum hold time fo r resetting is 1 s. disables the oscillator when active. high 19 br/d baud rate control/data br/d = 0, data communication mode: rs232 txd data line is connected (via a level shi fter) to td_232 input pin. the txd - signal is appropriately shortened and applied to the out put td_ir, driving the txd input of the ir transceiver. the rxd line of the transceiver is connected to the rd_ir input. this signal is stretched to the correct bit length according to the programmed bit rate and is routed to the rs232 rxd line at the rd_232 pin. br/d = 1, programming mode: data received from the rs232 port is interp reted as control word. the control word programs the baud rate width will be effective as soon as br/d return to low. 6, 8 , 11, 15, 20 nc td_232 rd_232 br/d reset td_ir rd_ir td_led rd_led v cc_sd s2 s1 g n d x1 x2 v cc oscillator endec ba u d generator logic 18079
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 3 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 operation description the block diagram shows a ty pical example of an rs232 port interface. the TOIM5232 connects to an rs232 level converter on one side, and an infrared transceiver on the other. the internal TOIM5232 baud rate generator can be software controlled. ? when br/d = 0, the TOIM5232 interprets the channels td_232 to td_ir and rd_ir to rd_232 as data channels. ? on the other hand, whenever br/d = 1, the TOIM5232 interprets td_232 as control wo rd for setting the baud rate. the baud rate can be progra mmed to operate from 1200 bit/s to 115.2 kbit/s. as rs232 level converter, eia232 or max232 or equivalent are recommended. ? when using the TOIM5232 directly connected to an uart it is compatible to 5 v ttl and 3.3 v cmos logic. ? typical external resistors and capacitors are needed as shown in the tfdu4...,tfbs4...-series references. ? the output pulse duration can also be programmed, see chapter operation description . it is strongly recommended using 1.627 s output pulses to save battery power. as frequency determining component a vishay xt49m crystal is recommended, when no external clock is available. ? ? ? we strongly recommend no t to use this 3/16 mode because 3/16 pulse length at lower bit rates consumes more power than the shorter pulse. at a data rate of 9600 bit/s, the ratio of power consumption of both modes is a factor of 12 (!) programming the TOIM5232 for correct data rate depend ent timing the TOIM5232 is using a built-in baud rate genera tor. this is used when no external clock is not available as in rs232 ir-dongle applications. for programming the br/d pin ha s to be set active, br/d = 1. ? in this case the TOIM5232 in terprets the 7 lsbs at the td_232 input as a co ntrol word. the operating baud rate will change to its supposedly ne w baud rate when the br/d returns back to low (0) set the uart to 8 bit, no parity, 1 stop bit. absolute maximum ratings parameter symbol min. typ. max. unit notes supply voltage v cc - 0.5 3.6 v input voltage - 0.5 5.5 v all pins output voltage - 0.5 v cc + 0.5 v all pins output sinking current i out 8 ma all pins junction temperature t j 125 c ambient temperature (operating) t amb - 25 8 5c storage temperature t stg - 25 8 5c soldering temperature t sldr 260 c dc characteristics parameter test conditions symbol min. typ. max. unit operating voltage v cc 2.7 3.3 3.6 v v cc = 3.3 v 5 %, operating temperature = - 25 c to + 85 c input high voltage inputs tolerate levels as high as 5.5 v maximum. all inputs are schmitt trigger inputs v ih 2 v input low voltage v il 0. 8v input schmitt trigger hysteresis v hyst 0.6 v input leakage no pull-up/down v in = v cc or gnd i l - 10 1 10 a output high voltage i oh = - 2 ma v oh 2 v i oh = - 0.5 ma v oh 2.4 v output low voltage i ol = + 2 ma v ol 0.4 v consumption current standby inputs grounded, no output load v cc = 3.3 v, t = 25 c i sb 1a consumption current dynamic inputs grounded, no output load v cc = 3.3 v, t = 25 c i cc 2ma
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 4 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 x: do not care ? s1, s2: user programmable bit to program the outputs s1 and s2 ? s0: irda pulse select ? s0 = (1): 1.627 s output pulses ? s0 = (0): 3/16 bit time pulses, not recommended ? b0 to b3: baud rate select words according following table. example: ? to set TOIM5232 at com2 port (2f8) to 9600 bit/s with 3/16 bit time pulse duration send to the TOIM5232 in programming mode in e.g. basic ? out &h2f8, (&h6) ? for same port, 9600 bit/s and 1.627 s pulse duration send ? out &h2f8, (&h16) ? for additionally activating s1 send ? out &h2f8, (&h36) note irda standard only supports 2.4 kbit/s, 9.6 kbit/s, 19.2 kbit/s, 57.6 kbit/s, and 115.2 kbit/s (3.6864 mhz clock). doubling the baud rates is allowed by doubling the clock frequency. software for the toim4232 and TOIM5232 uart programming for proper operation, the rs232 must be programmed (using 8 bit, 1 stop, no parity) to send a two character control word, yz. the control word yz is composed of two ch aracters, written in hexadecimal, in format: yz. the transfer rate for programming must be identical with the formerly programmed data rate, or after resetting the TOIM5232, the default rate of 9600 bit/s is us ed. note ? it is recommended reading the i/o buffer after transmission wa iting the specified latency allowance. that avoids receiving une xpected data from pulses stochastically generated by many transceivers during the latency time. (1) for programming the uart, refer to e.g., national semiconductors datasheet of pc 16550 uart. control byte (8 bit) first character second character x s2s1s0b3b2b1b0 lsb baud rate select words b3 b2 b1 b0 2 nd char baud rate 00000 115.2 khz 00011 57.6 khz 00102 38.4 khz 00113 19.2 khz 01004 14.4 khz 01015 12.8 khz 01106 9.6 khz 01117 7.2 khz 10008 4.8 khz 10019 3.6 khz 1010a 2.4 khz 1011b 1.8 khz 1100c 1.2 khz step. reset br/d td_uart rd_uart rd_ir td_ir description and comments 1highx x x x x resets all internal re gisters. resets to irda default data rate of 9600 bit/s 2lowx x x x x wait at least 2 ms, to allow start-up of internal clock. when external clock is used: wait at least 7 s. 3lowhigh x x x x wait at least 7 s. TOIM5232 now is set to the control word programming mode 4lowhigh yz with y = 1: 1.627 s y = 0 3/16 bit length xxx sending the control word yz. examples: send 1z if 1.627 s pulses are intended to be used. otherwise send 0z for 3/16 bit period pulses. y6 keeps the 9.6 kbit/s da ta rate. z = 0 sets to 115.2 kbit/s, see programming table. wait at least 1 s for hold-time. 5 low low data data data data with br/d = 0, TOIM5232 is in the data communication mode. both reset and br/d must be kept low (0) during data transmission. reprogramming to a new data rate can be re sumed by restarting from step 3. the uart itself also must set to the correc t data rate (1) .
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 5 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 recommended application circuit for TOIM5232 application circuit using tfdu4301 with integrated level shifter ma x3232cse. when used directly with 3 v - or 5 v - logic, the level shifter can be omitted. r4 c3 j1 co n 9 1 2 3 4 5 6 7 8 9 tfdu4301 + c10 c4 z2 u1 max3232cse 13 8 11 10 1 3 4 5 2 6 12 9 14 7 16 15 r1i n r2i n t1i n t2i n c+ c1- c2+ c2- v+ v- r1out r2out t1out t2out v cc g n d + c8 external inp u t 3.6 v max. optional TOIM5232 c5 r1 rxd dtr (reset) j2 co n 2 1 2 vcc u3 2 4 6 8 5 3 1 7 cathode rxd vcc1 g n d sd txd anode v log + + *) n c: 6, 8, 11, 15, 20 u2 18 19 1 2 3 4 5 7 9 16 14 13 12 *) 10 17 reset br/d rd_232 td_232 v cc_sd x1 x2 g n d td_led rd_ir td_ir s2 s1 n c rd_led v cc r2 c11 rts (br/d) c7 c6 txd c9 y1 c1 + ired z1 r3 + ired + c2 20799 recommended application circuit components component recommended value vishay part number 1. c1 100 nf vj 1206 y 104 j xxmt 2. c2 10 f, 16 v 293d 106x9 016b 2t 3. c3 100 nf vj 1206 y 104 j xxmt 4. c4 100 nf vj 1206 y 104 j xxmt 5. c5 100 nf vj 1206 y 104 j xxmt 6. c6 100 nf vj 1206 y 104 j xxmt 7. c7 1 f, 16 v 293d 105x9 016a 2t 8. c8 22 pf vj 1206 a 220 j xamt 9. c9 22 pf vj 1206 a 220 j xamt 10. c10 6.8 f, 16 v (optional) 293d 685x9 016b 2t 11. c11 100 nf vj 1206 y 104 j xxmt 12. z1 3.6 v bzt55c3v6 13. z2 3.6 v bzt55c3v6 14. r1 5.6 k ? crcw-1206-5601-f-rt1 15. r2 100 k ? crcw-1206-1003-f-rt1 16. r3 47 ? crcw-1206-47r0-f-rt1 17. r4 27 ? (for reduced current only) crcw-1206-27r0-f-rt1 18. y1 3.686400 mhz xt49s - 20 - 3.686400m 19. u1 max 3232cse maxim max 3232cse 20. u2 TOIM5232 21. u3 tfdu4301 22. j1 9 pin - connector cannon 23. j2 power connector philmore phi 211b
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 6 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package dimensions in millimeters reel dimensions in millimeters 20797 recommanded footprint pin 1 id 4.3 2 0.3 0.55 0.5 0.55 4.3 0.3 14017 dra w ing- n o.: 9.800-5090.01-4 iss u e: 1; 29.11.05 tape width (mm) a max. (mm) n (mm) w 1 min. (mm) w 2 max. (mm) w 3 min. (mm) w 3 max. (mm) 12 330 50 12.4 22.4 11.9 15.4
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 7 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 tape dimensions in millimeters 20798
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 8 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 toim4232 (TOIM5232) encoder - decoder interface ? programming and data transmission operation and programming of the toim4232 and TOIM5232 interface devices are described below. figure 1 shows the basic circuit design with 3 blocks: the rs232 to 3 v logic level shifter, the encoder/decoder (e ndec) circuit and the transceiver to buil d a dongle for rs232 irda extension. u1 is the level shifter to convert the rs232 logic levels to unipolar 3 v logic; u2 is the encoder/decoder interface (endec) converting the nrz - rs232 logic to irda rzi - logic. the transceiver u3 transmits and receives irda-compliant optical signals. fig. 1 - circuit diagram of the demo board circuit description this circuit demonstrates the operation of an sir irda transceiver module. the transceiver u3 (e.g., as shown the tfdu4101 or tfdu4301 or any other) converts the digital electrical input signal to an optical output signal to be transmitted, receives the optical signal, and converts these to electrical digital signals. while the irda physical layer protocol transmits only the 0 represented by a pulse with a return to zero inverted (rzi) logic, the rs232 protocol needs a no return to zero (nrz) representation. this decoding/encoding process is done by u2, an interface circuit stretching the received pulses and shortening the pulses to be transmitted according to the irda physical layer conditions. u1 interfaces the rs232 logic bipolar levels to the 3 v logic of the endec u2. the board is connected by con9 to the rs232 port (of a computer or other equipment. the basic irda transmission spee d is 9600 bit/s. this is the default state of the endec in power-on condition. also, activating the reset line at pin 1 (18) will set the device to this basic state. ? note: the first pin number refers to toim4232; the second number in brackets refers to TOIM5232. the crystal y1 controls the timing of the endec as a clock reference. the outputs s1 and s2 are progr ammable output s for control operations and the outputs rd_led and td_led can drive leds for indicating data flow. programming the endec for decoding data rates other th an the default, the endec is to be programmed to set the in ternal counters and timers. to switch the endec from the data transfer mode to the bit rate programming mode, the in put br/d, pin 2 (19) is set active high (br/d = 1). in this case the TOIM5232 interprets the 7 lsbs at the td_232 input as a control word. the operating bit rate will chan ge to its supposedly new rate when the br/d returns back to low (0). set the uart to 8 bit, no parity, 1 stop bit. ? the control byte consists of 8 bit after the start bit (sta, which is 0). keep in mind th at the order is lsb first, msb last. ? the diagram in figure 2 sh ows the programming byte 0-1010-1100 in the order sta, b0, b1, b2, b3, s0, s1, s2, x. this order is from right to left in table 1. b0 is sent first as lsb (see figure 2). ? the four least significant bits are responsible for the data rate according to table 2 while the four higher bits are for setting the irda pulse duration (s0), and the two outputs of the endec s1 and s2. bit 8 is not used. rxd txd rts (br/d) u3 tfdu4101 2 4 6 8 5 3 1 7 cathode rxd vcc1 gnd sd txd a node . c3 j1 con9 1 2 3 4 5 6 7 8 9 c6 c5 u2 toim4232 1(18) 2(19) 3(1) 4(2) 5(3) 6(4) 7(5) 8(7) 9(9) 15 ( 16 ) 14(14) 13(13) 12(12) 11 *) 10(10) 16(17) reset br/d rd_232 td_232 vcc_sd x1 x2 gnd td_led rd_ir td_ir s2 s1 nc rd_led vcc c7 u1 max3232 13 8 11 10 1 3 4 5 2 6 12 9 14 7 16 15 r1in r2in t1in t2in c+ c1 - c2+ c2 - v+ v - r1out r2out t1out t2out vc c gnd c8 c9 r2 z2 r1 + c2 c1 y1 j2 co n 2 1 2 r4 c4 r3 c11 + c10 external inp u t 3.6v max. dtr (reset) + + (TOIM5232) tfdu4301 optional tfdu4300:vlog tfdu4101: n c this line not u sed fot tfdu4101 ired ired + + + vcc *) (6), (8), (11), (15), (20) 21046
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 9 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note x: do not care ? s1, s2: user-programmable bit to program the outputs s1 and s2. in the example, s1 is set active, and s2 is inactive. ? s0: irda pulse select ? s0 = (1): 1.627 s output ? s0 = (0): 3/16 bit time pulses, not recommended ? b0 to b3: baud rate select words according to the following table below. notes bold: see example ? irda standard only supports 2.4 kb it/s, 9.6 kbit/s, 19.2 kbit/s, 57.6 kbit/s, and 115.2 kbit/s (3.6 8 64 mhz clock). doubling the baud rates is permissible by doubling the clock frequency. in figure 2 the programming sequence is shown for a bit rate of 12. 8 kbit/s. fig. 2 - programming sequence fo r setting the endec to a bit rate of 12.8 kbit/s. after setting br/d high (ch1), the programming sequence with the contro l byte (ch2) is appl ied to td_232, pin 4. fig. 3 - programming sequence for setting the endec to a bit rate of 12.8 kbit/s as in figure 2 but with a 3/16 bit pulse du ration (s0 = 0). when correctly programmed, th e endec shortens the pulse to be transmitted from the full bi t duration to either 3/16 of the bit length or to 1.627 s (which is 3/16 of the 115.2 kbit/s bit duration). for power saving, the short pulse is recommended. ? the received optical pulse shows in case of most of the v ishay sir transceivers, consta nt pulse duration. the endec stretches that to the correct bit time according the bit rate setting. this is shown in the following chapters. table 1 - control byte (8 bit) first character second character sta x s2 s1 s0 b3 b2 b1 b0 0 msb lsb example 0 011 01 01 0 in the oscilloscope that will be shown in the reserved order with lsb first, see figure 2. sta first character second character 0 b0 b1 b2 b3 s0 s1 s2 x lsb msb example 01 01 011 0 0 table 2 - transmission rate select words b3 b2 b1 b1 hex bit rate 0 0 0 0 0 115.2 khz 0 0 011 57.6 khz 0 01 02 3 8 .4 khz 0 0113 19.2 khz 01 0 0 4 14.4 khz 01 0 1 5 12.8 k hz 011 0 6 9.6 khz 01117 7.2 khz 1 0 0 0 8 4. 8 khz 1 0 0 1 9 3.6 khz 1 010a 2.4 khz 1 011b 1. 8 khz 11 0 0 c 1.2 khz example 0 01 0 0 1 01 0 msb lsb sta 1-> 2-> 21038 1) ch1: br/d; pin 2, v ertical scale: 2 v/di v ., horizontal scale: 200 s/di v . 2) ch2: td_232; pin 4; programming se qu ence 1-> 2-> 1) ch1: br/d, pin 2, v ertical scale: 2 v/di v ., horizontal scale: 200 s/di v . 2) ch2: td_232, pin 4; programming se qu ence 21030 sta 1 0 1 0 0 1 0 0
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 10 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 transmit (txd) channel figure 4 shows the transmissi on in the default mode. for data transfer, the endec is set to that mode by br/d = 0. in the examples 6 is always transmitted (binary 00000110). the 0 is represented in the irda protocol by an optical pulse. also here the lsb is transmitted first after the start bit. 1 is not transmitted. fig. 4 - data transmission with 9.6 kbit/s,1.627 s pulse duration channel 1 shows the signal from the rs232 port already converted to 3 v logic by u1. the endec encodes that signal to the rzi irda format where a 0 is represented by a pulse. that is the trace of channel 2. this output is connected the txd input of the transceiver and this signal is transmitted as optical output signal. channel 3 is the signal for an indicator lamp connected to the td_led driver output. use 180 ? serial resistor to supply vo ltage for limiting the current through the led (not shown in the circuit diagram). ? when using the (not recommend ed) 3/16-bit pulse width the oscillogram looks like figure 5. fig. 5 - data transmission with the setting 9.6 kbit/s, 3/16 bit pulse duration (19.5 s) the transmission with the highest sir bit rate of 115.2 bit/s looks like what is shown in figure 6. however, the horizontal time scale is different. fig. 6 - data transmission with the setting 115.2 kbit/s, 1.627 s pulse duration. by definition, th e pulse duration of 1.627 s is identical to the 3/16-bit pulse width. receive (rxd) channel in the default 9600 bit/s mode the signals will look like those shown in figure 7 and figure 8. fig. 7 - data reception wi th the setting 9.6 kbit/s. short rxd pulse fig. 8 - data reception wi th the setting 9.6 kbit/s. same as in figure 7, extended pulse duration the endec stretches the received pulses of about 2 s duration from the transceiver output (figure 7, channel 1) independent of the pulse duration to the full bit width generating nrz code (channel 2). channel 3 is the signal for the indicator lamp. ? as shown in figure 8 , channels 2 and 3, the final nrz signal is identical to figure 7, even when longer pulses are received. ? in the 115.2 kbit/s mode the si gnals will look like those shown 1-> t 2-> 3-> 21031 sta 0 1 1 0 0 0 0 0 1) ch1: td_232 inp. pin 4, v ertical scale: 2 v/di v ., horizontal scale: 200 s/di v . 2) ch2: td_ir, pin 14; 1.6 s p u lse d u ration 3) ch3: td_led, pin 9 1-> 2-> 3-> 21032 1) ch1: td_232, pin 4, v ertical scale: 2 v/di v ., horizontal scale: 200 s/di v . 2) ch2: td_ir, pin 14; 3/16 b it p u lse d u ration 3) ch3: td_led, pin 9 3-> 1-> 2-> 21033 1) ch1: td_232, pin 4, v ertical scale: 2 v/di v ., horizontal scale: 20 s/di v . 2) ch2: td_ir, pin 14; 1.6 s p u lse d u ration 3) ch3: td_led, pin 9 1-> 2-> 3-> 21034 1) ch1: toim4232; rd_ir, pin 15, v ertical scale: 2 v/di v ., horizontal scale: 200 s/di v . 2) ch2: toim4232; rd_232, pin 3 3) ch3: toim4232; rd_led, pin 10 1-> 2-> 3-> 1) ch1: toim4232; rd_ir, pin 15, v ertical scale: 2 v/di v ., horizontal scale: 200 s/di v . 2) ch2: toim4232; rd_232, pin 3 3) ch3: toim4232; rd_led, pin 10 21035
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 11 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 in figure 7 and figure 8 . the difference is just the time scale. it also indicates the delay of the decoded channel 2 vs. channel 1. fig. 9 - data reception with the setting 115.2 kbit/s channel 1 shows the signal from the transceiver. in this case it is tfdu4101 with unsymme trical switching times. tfdu4101 is using tri-state ou tputs with push-pull drivers with symmetrical pulse switching times. all v ishay irda transceivers exhibit constant output pulse duration in sir mode of about 2 s independent of the duration of the optical input pulse. ? ? ? ? ? echo-on or echo-off and latency allowance during transmission, the receiver inside a transceiver package is exposed to very strong irradiance of the transmitter, which causes overload conditions in the receiver circuit. after transmission it takes some time to recover from this condition and return to the specified sensitivity. ? during this time the receiver is in an unstable condition, and at the output unexpected signals may arise. also, during transmission under overload conditions the receiver may show signals on the rxd channel that are similar to or identical with the transmitted signal. to get clean or at least specified conditions for the receive channel during transmission, different terms were defined. the time to allow the receiver to recover from overload conditions is the latency allowance or shorter, ju st the specified latency. this is covered by the irda physica l layer specification and is a maximum of 10 ms. irda sp ecifies shorter negotiable latency. in sir the minimum is 0.5 ms. this includes software latency. tr ansceivers are in general below 0.3 ms. ? in the first generations, some suppliers did not care for the behavior of the rxd output of the transceivers during transmission and latency time. the software is able to handle that. the easiest way is to clean up the receiver channel after sending the last pulse and waiting for the latency period. ? later, many transcei vers that block the rxd channel during transmission and during the late ncy period were released to the market. this behavior is called echo-off. unfortunately, some oems like to use the signal from the rxd channel during transmission, as a self-test feature for testing the device on board without using the optical domain. therefore, many new devices have been developed to echo the txd input signal at the rxd output. such behavior is called echo-on. ? some software developed for e cho-off applications is not able to receive and understand the signals from echo-on devices correctly. ? therefore, an add-on to the circuit shown in figure 1 was generated to suppress the echo from the receiver during transmission. this modification is shown in figure 10. ? during transmission, the signal from the rxd output of the transceiver is just gated by the transmit signal, (see the oscilloscope picture in figure 11). fig. 10 - demo board circuit with echo-suppression to be used for echo-on and echo-off transceivers. 1-> 2-> 3-> 21036 1) ch1: toim4232; rd_ir, pin 15, v ertical scale: 2 v/di v ., horizontal scale: 10 s/di v . 2) ch2: toim4232; rd_232, pin 3 3) ch3: toim4232; rd_led, pin 10 tfdu4300:vlog y1 c1 u2 toim4232*) 1 2 3 4 5 6 7 8 9 15 14 13 12 11 10 16 reset br/d rd_232 td_232 vcc_sd x1 x2 gnd td_led rd_ir td_ir s2 s1 nc rd_led vcc r3 + c10 txd rxd r5 u4 dg2039 1 4 8 3 7 2 6 5 nc_1 d v+ ins2 ins1 com_1 com_2 no_2 c8 dtr (reset) vcc + c2 external input 3.6v max. u1 max3232 13 8 11 10 1 3 5 2 6 12 9 14 7 16 15 r1in r2in t1in t2in c+ c1- c2+ c2- v+ v- r1out r2out t1out t2out vcc optional + u3 tfdu4101 2 4 6 8 5 3 1 7 cathode rxd vcc1 gnd sd txd anode . this line not used fortfdu4101 c6 + r2 c3 j2 co n 2 1 2 z2 c7 + + c11 j1 con9 1 2 3 4 5 6 7 8 9 pin7: tfdu4101:nc rts (br/d) tfdu4301 c5 c4 c9 z1 r1 + r4 *) for TOIM5232 pinning, see figure 1. 21047
TOIM5232 www.vishay.com vishay semiconductors rev. 1.3, 04-jul-12 12 document number: 81749 for technical questions within your region: irdasupportam@vishay.com , irdasupportap@vishay.com , irdasupporteu@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 additionally, with the programm able output s1 of the endec the echo suppression feature can be switched on and off for testing. the default mode is echo-off. to enable the echo, s1 is to be set inactive/low. (see the chapter for programming the toim4232, TOIM5232). ? the oscilloscope diagrams are shown in figure 11. channel 2 shows the echo signal on the rxd output of the tfdu4101 transceiver during transmission. ? channel 1 is the signal used for gating the path from the transceiver rxd output to the endec. on channel 3 the signal at the input of the endec is shown with a residual signal. finally, the output to the rs232 port, rd_232, is clean without any noise signal. fig. 11 - echo-suppression 1-> 2-> 3-> 4-> 21037 1) ch1: toim4232; td_232, pin 4, v ertical scale: 2 v/di v ., horizontal scale: 20 s/di v . 2) ch2: tfdu4101; rxd, pin 4 (ir) 3) ch3: toim4232; rd_ir, pin 15 4) ch4: toim4232; rd_232, pin 3
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